Digit By Digit Fast Decimal Multiplication

This paper proposes a novel Radix-10 fixed point multiplier for multiplying two unsigned single digit operands. The design can also form the integral multiplication unit of IEEE 754-2008 decimal64 compliant floating point multiplier architecture. Of the sixteen Vedic Sutras, Nikhilam Sutra has been used for generation and accumulation of the partial products respectively. The multiplier employs a novel reduced magnitude partial product generator which recodes the two individual digits in the multiplier and multiplicand so that at least one of them belongs to the reduced digit set [1], [5]. The multiplier architecture is purely combinational in nature. The theoretical critical path logic level delay calculations excel over existing counterparts.