Power Aware Study of 32-bit 5-stage Pipeline RISC CPU using 180nm CMOS Technology

In this work, the 5-stage pipeline 32-bit RISC CPU has been designed and the power consumption of CPU is investigated. The total power consumption of the CPU has been obtained using the standard cells of SCL 180 nm CMOS technology. The pre-layout and post-layout simulation results for the CPU are analyzed. The effective switching capacitance values are compared for pre-layout and post-layout design. The impact of clock gating technique on the power consumption of CPU is analyzed. From the results it has been observed that the power consumption of CPU can be reduced by 23% after applying clock-gating technique to the 5-stage pipeline CPU. From the post layout simulation results it can be seen that the effective switching capacitance can be reduced by 23% by using clock gating method which is same as the value of power saving.