Hybrid Doped PMOS and its Short Channel Performance

In this work a hybrid doped p type MOSFET is proposed. The structure has two gates, a main gate (MG) and a side gate (SG). The main gate controls channel conductivity of the transistor similar to the conventional MOSFET gate electrode while the side gate induces substrate doping electrically. In the proposed structure source region is doped conventionally whereas doping of the drain region is controlled electrically by varying voltage at the SG. A zero or negative voltage on the SG induces a p-type drain region underneath it. Further, doping level of the region can also be controlled by varying SG work function and its length. An optimum value for the SG work function is selected to provide the maximum I
_ON
/l
_OFF
current ratio. We have observed reduced peak electrical on the drain-channel junction which improves various short channel effects in the proposed device. The 2D calibrated simulation reveals that the threshold voltage (V
_TH
) roll-off, drain induced barrier lowering (DIBL), subthreshold slope (SS) and I
_ON
/I
_OFF
ratio are significantly improved in comparison to the conventional SOI MOSFET. These effects are simulated along with their conventional device counterpart.