Design of an Enhanced Array Based Approximate Arithmetic Computing Model for Multipliers and Squarers

Exact circuits produce accurate results but consume more power and area. Approximation is done to reduce the high consumption of area and power at the cost of accuracy. An array-based approximate arithmetic computing model (AAAC) is used for the reduction of error occurring in approximate binary arithmetic circuits. Although the model provides a trade-off between power, area and accuracy, these parameters can be improved further. The proposed model in this paper uses reduced number of truncated bits and a different compressor architecture for this improvement. An approximate 16 ×16 booth multiplier and an approximate 16 bit squarer are used as the applications. The proposed model for squarers reduce the power and area by 8.4% and 21.5% respectively and has an accuracy improvement of 3.4% when compared to the existing model. Similarly the proposed model for booth multiplier reduces the power and area by 4.5% and 3% respectively and has an accuracy improvement of 3.2% when compared with the existing one.