Design of a High-speed Reconfigurable Fast Hartley Transform Processor using CBNS

This paper proposes a high speed Fast Hartley Transform (FHT) processor using Complex Binary Number System (CBNS). The proposed FHT architecture with the properties of modularity and scalability is well suited for VLSI implementation. The arithmetic computational modules of CBNS-FHT are coded in VHDL through structural modeling style. Simulation of proposed CBNS-FHT processor has been performed on FPGA XC3S700A platform using Xilinx ISE Design Suite 13.4. Comparative analysis of CBNS-FHT with Normal Binary Number System (NBNS)-FHT has been carried out in terms of combinational path delay. Significant improvement in path delay has been observed in CBNS-FHT processor both in terms of FHT coefficients as well as the size of the FHT, leading to the design of a high speed FHT processor.