A Novel Comparator Offset Calibration Technique for SAR ADCs

This paper proposes a novel comparator offset calibration technique for SAR ADCs. We realize the calibration in CDAC instead of the comparator circuit, so that the power consumption, area and circuit complexity barely increase, which is a big advantage compared to traditional ones. A 10-bit 100Msps SAR ADC applying our offset calibration is designed in a 55nm CMOS process. The post simulation results show that the ENOB achieves 9.5 bits and consumes a power of 4.4mW at the sampling rate of 100MHz.