Analysis of Gate Current Wafer Level Variability in Advanced FD-SOI MOSFETs

This work explores, for the first time, wafer level variability of the gate leakage current in advanced FD-SOI MOSFETs. A simple model based on WKB approximation is introduced to model the leakage current and its variance. IL/HK variability segregation is presented using split C-V and gate current data without any dedicated test structures.