Performance Characterization and Majority Gate Design for MESO-Based Circuits

Magnetoelectric spin-orbit (MESO) logic is a promising spin-based post-CMOS logic computation paradigm. This paper explores the application of the basic MESO device concept to more complex logic structures. A simulation framework is first developed to facilitate the performance evaluation of MESO-based circuits. Based on the analysis, it is seen that inadvertent logic errors may potentially be introduced in cascaded MESO stages due to sneak paths, and solutions for overcoming this problem with a short pulse and two-phase evaluation are discussed. Next, the generalization of the MESO inverter structure to majority logic gates is shown. Two implementations, based on different physical mechanisms, are presented and a relative analysis of their speed and power characteristics is provided.