Effect of Chip Layout in Wafer on Molding and Fan-Out Wafer Level Packaging (FO-WLP) Technology

Fan-out wafer-level packaging (FO-WLP) technology including molding and RDL process is attracting more and more attention due to its low cost, high performance and flexibility. But for the Die-First process, the wafer warpage and expansion in process are always the most critical keys to FO-WLP technology, which will affect the RDL accuracy. In this paper, the influence of chip layout in 12'' wafer on warpage and expansion was studied by simulation and experiment. The warpage includes two aspects: the first in molding and the second in RDL process. The expansion was mainly due to RDL process. Chip layout has great influence on warpage and expansion when the chip thickness and the wafer thickness were fixed. Through the research of four typical layouts, we found the rules and gave some useful suggestions about layout.