Component Failure Analysis (CFA): A New Method for Implemented FPGA Design Failure Analysis

FPGAs are reconfigurable hardware architectures that have been used in implementing safety-critical embedded systems where failure analysis is required. Single Event Upset (SEU) in digital electronics is one of the critical safety hazards in digital electronics. The effect of SEUs must be analyzed according to the system functional safety. The SEU failure analysis is one of the well-established research topics due to the continuous shrinking size of new IC technology and the growing risk of SEU failure. This paper introduces a new probabilistic method, the Component Failure Analysis (CFA), that uses FPGA specific techniques and algorithms for analyzing SEUs in implemented FPGA designs. The CFA focuses on providing an early insight to the designer about the implemented design during the product development phase. This paper provides step by step illustrative examples and several tests to verify and validate the performance of CFA on FPGA implemented benchmark circuits. From these tests, CFA is observed to have a faster computation time as well as high accuracy. In this work, Xilinx FPGAs have been investigated, but the method can be easily extended to cover other reconfigurable digital systems.