Automated Verification System for Functional Coverage Extraction

With the increasing complexities of semiconductor designs, verification becomes more critical and time consuming. ASIC verification consumes 60 to 70 percent of the entire product cycle and hence it is a very important task in digital design world. To reduce the overall time to market, it is crucial to complete the verification in a narrow time frame. Coverage gives the statistical measure of the verification objectives that have been met. The objective of this paper is to automate the creation of coverage model from the coverage plan, thus reducing the verification efforts and increasing the verification productivity.