Write Disturb in Ferroelectric FETs and Its Implication for 1T-FeFET AND Memory Arrays

In this letter, the write disturb of Hf_0.5Zr_0.5O₂-based 1T-FeFET nonvolatile AND memory array is experimentally investigated for V_W/2 and V_W/3 inhibition bias schemes to determine the worst-case memory sensing condition. Read margin analysis reveals that the increased leakage current in the low-V_TH erased state and the increased read current of the high-V_TH programmed state are the key factors that limit the maximum array size.