A Fast Locking Phase-Locked Loop with Low Reference Spur

This paper presents a 3.2GHz dual loop PLL suitable for WiMAX applications which offers high speed locking, low reference spur, and low power consumption. We utilized Aperture Phase Detection (APD) mechanism in order to be able to turn off the blocks associated with frequency locked loop (FLL) in locked state, thereby reducing the overall power consumption. In the proposed dual-loop PLL, we adopted a new technique to decrease the dead zone (DZ) in DZ-creator circuit and speed up the frequency locking. Accordingly, a fast locking PLL is achieved. In addition, a modified variable amplitude Charge Pump (CP) is incorporated to reduce the reference spur. To evaluate the proposed techniques, we simulated the designed PLL by using the foundry design kit for
$0.18\mu\text{m}$
CMOS technology through ADS simulator. The spur level and lock time of the proposed circuit is −74dBc and
$1.9 \mu\text{s}$
, respectively, indicating 5dB improvement in spur level and 32% improvement in lock time, compared with previously proposed circuits. The power consumption of the proposed circuit is 4.15 mW.