A High Data Rate Pipelined Architecture of AES Encryption/Decryption in Storage Area Networks

AES algorithm is one of the most popular encryption algorithms. Various means of AES algorithm implementation on FPGA attributed to the application and internal blocks complexity. In this study, we have analyzed different blocks of AES algorithm and proposed a model for its FPGA implementation of encryption/decryption parts. Pipeline structure is employed for achieving High throughput as well as diminished area extent. To reach desired throughput rate of AES algorithm in data storage network, a combined approach of memory utilization with $\text{GF}(2^{4})$ is applied. Special multiplexer based architecture is employed underlain S-Box block to attain least possible slices. Synthesize output of Encryption/Decryption implementation on Xilinx Virtex5, 60Gb/s throughput and 460 MHz operational frequency, represent superior results in presence with best previous works.