On the design of a fourth-order continuous-time LC delta-sigma modulator for UHF A/D conversion

We consider the design and test of a fourth-order bandpass delta-sigma modulator (/spl Delta//spl Sigma/M) for conversion of UHF analog signals to the digital domain for heterodyning and processing there. A prototype modulator in 0.5-/spl mu/m SiGe presented in the second part of the paper achieved 40 dB of dynamic range in a 20-MHz bandwidth centered at 1 GHz and consumed 450 mW from a single 5-V supply. At the time this modulator was designed, no explicit design procedure to achieve a certain modulator performance level had been established. The first part of this paper, therefore, is devoted to explaining the tradeoffs involved in choosing the parameters for a gigahertz-clocking transconductor/LC-based /spl Delta//spl Sigma/M and formulating such an explicit design procedure. Finally, we elucidate some further design considerations, redesign the prototype to improve its simulated performance, and discuss the general appropriateness of high-speed continuous-time /spl Delta//spl Sigma/M for UHF analog-to-digital conversion.