Second-Harmonic Power Generation Limits in Harmonic Oscillators

Based on piecewise linear modeling of field-effect transistors, harmonic translations are deployed to analyze the fundamental limits for a maximum second-harmonic power generation for any given field-effect transistor. Optimum waveforms at the gate-source and drain-source terminals, which yield high second-harmonic power generation by the given transistor, are derived. Two oscillators are implemented in a TSMC 65-nm CMOS process. Transistors in these oscillators have optimum voltage waveforms at their terminals. Thus, they deliver a state-of-the-art second-harmonic output power while operating at relatively higher frequencies than related arts. One of the proposed oscillators has the maximum output power of 4.9 dBm and a peak dc-to-RF efficiency of 3% at 300 GHz. Each of the implemented oscillators occupies 0.16 mm
²
of the chip area.