Design and Implementation of an All Digital Phase-Locked Loop which Responds Dynamically to Reference Frequency whose Value Varies in a Wide Range

To remove the problems of most current all digital phase-locked loops (ADPLLs) on narrow phase locked range, poor versatility, and difficult approaches to on-line adjustment of system parameters, an All Digital Phase-locked Loop with Automatic Measure and Control is proposed. It adjusts dynamically the parameters of the subsystem controllable divider according to frequency variation of the input signal detected by a module which implements automatic measure and control of reference frequency. It brings the proposed system many changes such as variable center frequency, which in turn expands frequency-locked range, and improves phaselocked speed. Similarly, the parameters of the digital filter can also be dynamically adjusted on detecting the variation of phase as well as frequency difference of the input signal, and as a result, phase-locked speed is accelerated, while phase jitter is reduced. The system design was completed with Quartus II , and the system performance was verified through computer simulation as well as FPGA-based experiment. The results show that the proposed DPLL runs well with a wide phase locked range, high phase locked speed, outstanding system performance on stability, simple hardware implementation, and easy system level integration. It can be used as functional module that embedded into the system on a chip (SOC), and has a wide range of uses.