Algorithm and VLSI Architecture Design of Low-Power SPIHT Decoder for mHealth Applications

A real-time cost and power-efficient (CPE) set partitioning in hierarchical trees (SPIHT) decoder design with low hardware complexity and low-power dissipation is introduced in one-dimension (1-D) wavelet-based quality-assured electrocardiograph (ECG) compression systems for mobile health (mHealth) applications. However, current SPIHT coding architectures are designed for image/video processing. These architectures require a large amount of memory as well as complicated sorting algorithms, which both require time-consuming tasks and are unsuitable for mobile ECG applications. Based on our previously modified SPIHT coding work, which used flags and check bits to reduce memory requirements and coding complexity by merging three search processes into one step. Therefore, to achieve the real-time design goal for mobile ECG applications, in this paper, we first introduce a hardware-oriented SPIHT decoding algorithm that is suitable for decoding the previously presented SPIHT coding work. Accordingly, an appropriate low-power hardware architecture is developed to implement a real-time high-performance and low-cost SPIHT VLSI design for our proposed decoder algorithm, which is appropriate for mobile ECG applications. Using the distinct ECG signals in the MIT-BIH arrhythmia database (sampling rate of 360 Hz), the final simulation and VLSI implementation results reveal that the proposed CPE SPIHT decoder design outperforms the state-of-the-art designs in terms of the average decoding time, the decoding quality, the VLSI speed, and the power consumption. Most importantly, the design can be exploited to a 1-D 1024 × 1 wavelet-based quality-assured ECG data compression system.