Channel Engineered Cylindrical Double Gate All Around FET For Low Power VLSI Applications

A specific channel engineering over a cylindrical double gate all around FET (CDGAA FET) is proposed in this work. The engineering is to stack 3 layers of diversely doped silicon in channel region in order to attain a much better carrier concentration in all states of FET operation. This modified FET is termed as channel engineered cylindrical double gate all around FET (CE-CDGAA FET). The simulation results reveal that this modification provides reduced off current (Ioff), greatly enhanced on current (Ion) and boosts the on-off current ratio (Ion/Ioff). The proposed modification also lowers the drain induced barrier lowering (DIBL) and subthreshold swing (SS) compared to CDGAA FET. This evolution allows downscaling a FET up to 3nm channel length with acceptable performance in many of its performance parameters, marking its applicability in VLSI and low power FET applications. A comparative study between CE-CDGAA FET and CDGAA FET is also presented in this work.