Real Time SoC architectures for Analysis of EEG

Electroencephalography (EEG) is a multichannel non-stationary brain signal composed of multi-frequency. EEG signals are recorded with multiple electrodes either by scalp or intracranial method. It is well proven tool for brain disease detection or prediction. These brain signals are recorded with multiple electrodes with sampling rate. Thus the very huge data need to process and hence computationally intensive. Different architectures have been proposed and implemented to get high performance with accuracy from the device. This proposed work covers comparative study of different efficient architectures of the EEG signal analyzer and designs biosignal processor using FPGA by establishing link between FPGA and PC with URART serial link. More or less of the architectures of EEG signal processing are mainly used for seizure detection. The basic objective of this paper is to understand the implementation of real tiem EEG analyser using FPGA and SoC, to design simple bisignal processor for EEG analysis and analyze architectures based on different performance parameters like frequency of operation, peak power consumption, technology, memory size (bits), accuracy, ADC Resolution, chip area, gates/SRAM.