An SAR ADC Switching Scheme With MSB Prediction for a Wide Input Range and Reduced Reference Voltage

This paper proposes a new most significant bit (MSB)-prediction switching scheme and presents an energy-efficient successive approximation register (SAR) analog-to-digital converter (ADC) using the proposed scheme. The prediction of the MSB is conducted before the sampling phase, and the MSB-1 conversion switches all the capacitors of the capacitive digital-to-analog converter (CDAC) from the references set by the prediction result after the sampling phase. Therefore, the reference voltage in the proposed scheme is reduced by half to satisfy the same input range. Compared with the regular Vcm-based CDAC, the proposed technique exhibits a 75.1% reduction in switching energy and a reduction ratio of (1/2)
^1/2
in nonlinearity under the same capacitor area and matching condition. A 10-bit SAR ADC prototype is designed and simulated in a 180-nm CMOS process to validate the proposed technique. The ADC consumes $31.16~\mu \text{W}$ from a 1-V supply and the input range of [-2 V, 2 V]. The simulated signal-to-noise-and-distortion ratio is 61.01 dB at 2 MS/s, benefited from the redundant capacitors added to the CDAC.