A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18- $\mu$ m CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration

This paper proposes a time-to-digital converter (TDC) that achieves wide input range and fine time resolution at the same time. The proposed TDC utilizes pulse-shrinking (PS) scheme in the second stage for a fine resolution and two-step (TS) architecture for a wide range. The proposed PS TDC prevents an undesirable nonuniform shrinking rate issue in the conventional PS TDCs by utilizing a built-in offset pulse and an offset pulsewidth detection schemes. With several techniques, including a built-in coarse gain calibration mechanism, the proposed TS architecture overcomes a nonlinearity due to the signal propagation and gain mismatch between coarse and fine stages. The simulation results of the TDC implemented in a 0.18-μm standard CMOS technology demonstrate 2.0-ps resolution and 16-bit range that corresponds to ~130-ns input time interval with 0.08-mm
²
area. It operates at 3.3 MS/s with 18.0 mW from 1.8-V supply and achieves 1.44-ps single-shot precision.