A Novel Capacitor Sizing Method for Active DC Link Capacitance Reduction Circuit

The paper focuses on a novel capacitor sizing method for direct voltage regulated active capacitance reduction circuit. The aim of such a system is replacing the bulk DC bus capacitor without escalating the ripple. But the reduced capacitance implies a reduction on the storage energy, causing a large voltage drop during transients. The primary goal of the proposed method is to find the appropriate capacitor size to keep the voltage of the reduction circuit above a preset minimum voltage, even during transients. Mathematical analyses of the minimum capacitor voltage as well as the required capacitor size expression are presented. The revealed findings are fully supported by simulations and experimental results.