Efficient FPGA Implementation of Binary Field Multipliers Based on Irreducible Trinomials

Binary extension (or Galois) fields GF(2
^m
) have been widely studied due to their use in several important applications, such as cryptography, error control codes and digital signal processing. These applications require efficient hardware implementations of GF(2
^m
) arithmetic operations, particularly multiplication, which is considered the most important and complex one. The complexity of GF(2
^m
) multiplication depends on the representation basis and on the defining irreducible polynomial f(y) selected for the finite field. For efficient hardware implementations, polynomial basis and irreducible trinomials or pentanomials are normally used. Any element A ϵ GF(2
^m
) can be represented in the polynomial basis {1,x,...,x
^m-1
} as A = Σ
_i-0
^m-1
,α
_i
x
ⁱ
with α
_i
ϵ GF(2), where x is a root of the irreducible polynomial f(y) = Σ
_i=0
^m
f
_i
y
ⁱ
. Polynomial basis multiplication C = A · B requires a polynomial multiplication followed by a reduction modulo an irreducible polynomial. Mastrovito [1] proposed an efficient bit-parallel polynomial basis multiplier in which a product matrix was introduced to combine the above two steps together. A new polynomial basis multiplication method applied to irreducible trinomials was proposed in [2], where the functions S_i and T_i given by the addition of terms x
_k
= (a
_k
b
_k
) and z
_i
^j
= (a
_i
b
_j
+ a
_j
b
_i
), with a
_i
, b
_i
ϵ GF(2), were obtained from the decomposition of a product matrix. The addition of these functions is used for the computation of the product of two GF(2
^m
) elements. In [3], the above method was applied to type II irreducible pentanomials and the functions S_i and T_i were split in the form S
_i
= s
_k
ⁱ
S
_k
ⁱ
+ ... + s
₀
ⁱ
S
₀
ⁱ
and T
_i
= t
_k
ⁱ
T
_i
^k
+ ... + t
₀
ⁱ
T
_0i
, with s
_j
ⁱ
, t
_j
ⁱ
ϵ GF(2) and k = log
₂
m. The terms S
_i
^j
and T
_i
^j
represent the sum of 2
_j
products a_kb_l and therefore can be implemented as a j-level complete binary tree of XOR gates. The addition in pairs of binary trees with the same depth leads to a reduction of the multiplication delay. However, splitting method imposes hard restrictions (given by the use of parenthesis in the expressions of the coordinates) for the addition of S
_i
^j
and T
_i
^j
terms in order to reduce the number of XOR levels. These restrictions could not be efficient for a synthesis tool in order to map that expressions into FPGA's logic blocks. If parenthesized restrictions are removed, more freedom could be given for the synthesizer to find an optimized implementation of the multiplier. In this work, efficient Xilinx FPGA implementations of GF(2
^m
) bit-parallel polynomial basis multipliers for irreducible trinomials are presented. Based on [2], a new general algorithm for multiplication over irreducible trinomials f(y) = y
^m
+ y
ⁿ
+1, with 1 ≤ n ≤ (m+1)/2, is proposed and the splitting method given in [3] is applied to these irreducible polynomials. Furthermore, in order to optimize the synthesis of the multipliers, a new approach for the computation of the product is used where the splitting of S_i and T_i terms is performed, but the restriction given by the addition in pairs of binary trees with the same depth has been removed. In this way, Xilinx tools are free to optimize the synthesis of the multiplier. Several GF(2
^m
) multipliers for different binary fields have been described in VHDL and their post-place and route implementation results in Xilinx Artix-7 have been reported. Experimental results show that the multiplier here proposed exhibits the best delay and Area×Time complexities when it is compared with similar multipliers found in the literature. Moreover, the new approach also achieves the lowest number of slices in most of the implemented multipliers.