Multi-Level Approximate Accelerator Synthesis Under Voltage Island Constraints

Approximate computing forms a promising paradigm shift for energy efficient design by aggressively decreasing power consumption of inherently error-tolerant applications. However, approximate computing architectures exacerbate the design complexity due to the diversity of inexact techniques and their impact on final circuit implementations. In this brief, we introduce approximate accelerator synthesis, which enables the design of power-optimized inexact circuits under error bound constraints, by leveraging the incorporation of diverse multi-level approximate techniques. We show the high efficiency of adopting multi-level approximation techniques and present a systematic approach for integrating multi-level approximation in hardware accelerator synthesis under error bound and voltage island constraints.