A New Analytical Model for Predicting $dv/ dt$-Induced Low-Side MOSFET False Turn-ON in Synchronous Buck Converters

This paper presents new studies of dv/dt-induced low-side mosfet false trigger when the high-side mosfet is turned on in synchronous buck converters. New analytical expressions are derived and utilized to predict both the magnitude and duration of the false triggering pulse to reveal more physical insight into the phenomenon. In contrast to the existing simple analytical model, the new model takes into account effects of nonlinear time-varying nature of the low-side mosfet drain-to-source capacitance dv/dt, the low-side mosfet body-diode reverse-recovery current and common-source inductance during the entire high-side mosfet turn-on transition. On the other hand, unlike the high-order complex model, which can only be solved numerically, the proposed analytical model is expressed explicitly by a set of parasitic parameters, and consequently their effects on the low-side mosfet false trigger can be explored much more easily. The model is mostly suitable for low-voltage applications in which false turn-on of the low-side mosfet could happen more often than under high-voltage conditions due to lower mosfet gate threshold voltage and higher dv/dt. The model is tested on an experimental 12-1.35 V, 8 A synchronous buck converter, and predictions are compared with experimental data with favorable correlation.