Template architectures for highly scalable, many-core Heterogeneous SoC: Could-of-Chips

Heterogeneous Multi-Processor Systems-on-Chip (HMPSoC) are designed to support a wide variety of applications and need to be scalable to meet the different power/performance requirements. However, the amount of processing units and other mandatory resources such as memory, analogue blocks, existing hard and soft IP blocks make the design of such systems an extremely tedious task. As of today most of the HMPSoC architectures are implemented as integrated circuits using a single CMOS technology (i.e. homogeneous IC manufacturing process). This often results inefficiencies in Power, Performance, Area and thus Cost (PPAC), since the unique CMOS technology will need to compromise many orthogonal optimization objectives. In this paper we propose a new concept of system design that we call Cloud-of-Chips (CoC): a highly scalable and cost-efficient HMPSoC architecture using advanced IC packaging technologies such as 2.5 and 3D integration that allows to mix different CMOS processes into a single IC package. Further, CoC based architectures allow design configurability at various steps of system integration: at IC design-time, so during the system assembly, using chiplets and 3D stacking; and at run-time by adding a software configurable layer that can be used at system assembly step (e.g. at PCB level) of during software execution. CoC paradigm relies heavily on the concept of software controlled hierarchical interconnect, heavily inspired from already proven concept of Software Defined Networks.