A Novel Divisionless MT-Type Velocity Estimation Algorithm for Efficient FPGA Implementation

This paper deals with incremental encoder velocity estimation. More specifically, it addresses the computation issues of the well-known MT-method, used widely in advanced motion control applications. The MT-method calculus involves arithmetical division, which is a very unsuitable operation for digital implementation on real hardware, such as an FPGA. Thus, we propose a novel divisionless algorithm for velocity estimation. The proposed method possesses the advantages of both frequency count and period count methods as the well-known MT-method to produce reasonably accurate and smooth velocity signals in a wide speed range. However, its advantages in terms of simpler calculus make it significantly more suitable for a single-chip FPGA cost-effective solution. This paper presents the method and shows the results with simulation data and real encoder data acquired by practical digital circuit hardware. The shown results fully verify the proposed algorithm.