Deep Learning Accelerator on FPGA Using Handwritten Digit Recognition for Example

This paper presents an edge inference accelerator for deep learning application “Handwriting recognition” using field programmable gate array (FPGA). The parameter of the neuron network is trained using GPU and then download to an off-chip DRAM for the accelerator to access. The image data is transfered through Bluetooth from smart phone to the deep learning accelerator. This accelerator architecture can fit any neuron network and is suitable for consumer electronics such as IoT applications.