ASCGP - Automatic System for Construction of Logical Circuits in FPGA using CGP

In this article is introduced a novel framework for the development of an automatic system using a Cartesian Genetic Programming based approach to construct combinational and sequential logic circuits in FPGAs. The paper is comprised of two parts: the first one is based on a hybrid evolutionary algorithm that by means of parameters provided by the user looks for a logical circuit solution, and the second one is a flexible architecture developed in Verilog-HDL language that converts the solution given in the first part into a hardware implementation inside the FPGA. Good results using this hybrid evolutionary approach have been obtained in all the studied cases in relation to others similar studies in the literature. In addition, the generated hardware is able to manage sequential circuits, being this an innovation of the present project in relation to other projects found in the literature, in which almost all of them can only simulate the automatic generation of combinational circuits.