Fine-grain pipelined asynchronous adders for high-speed DSP applications

A new asynchronous pipeline scheme (called LP/sub w/), and two new pipelined asynchronous adder implementations, are introduced for high-throughput applications such as DSPs for multimedia processing. The pipeline scheme is targeted to dynamic datapaths. A novelty of the approach is that it uses decoupled control for pull-up and pull-down stacks. The adders are pipelined at the gate-level and achieve very high throughput: 930-1023 million additions per second in a 0.6/spl mu/ CMOS process. These results are expected to scale to several gigaoperations per second in more modern technologies.