Design and Implementation of Flexible and Reconfigurable SDF-Based FFT Chip Architecture With Changeable-Radix Processing Elements

In this paper, we propose a flexible and reconfigurable changeable-radix fast Fourier transform (FFT) hardware architecture. It aims to support 48 different FFT sizes and up to 4096 FFT points, which are defined in current 3GPP-LTE communication system. The built-up design structure is primarily constructed on a radix-5
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basis of single-path delay feedback FFT and up to 18 various changeable radixes of FFT processing. A design technique of switchable FIFO usage approach is developed to efficiently manage FIFO arrangement for 48 FFT modes. In addition, a design technique of coarse and fine rotating is designed to effectively reduce twiddle-factor circuit area. By using TSMC 40-nm CMOS technology, an FFT ASIC implementation only has a core area occupation of 0.414 mm
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and consumes 49.8 mW in average at maximal working frequency of 526.32 MHz. This innovative design work is competitive as compared to current state-of-the-art works, especially in terms of circuit area cost and power/energy performance evaluation.