A New Semi-Digital Low Power Low Jitter and Fast PLL in 0.18μm Technology

This paper presents a new semi-digital low power, low jitter and fast Phase-Locked Loop (PLL). The main advantages of the proposed PLL are to achieve high-speed, to generate non-overlap signal and to consume low power, reliably. The total power consumption of the proposed PLL in frequencies of 150MHz and 400MHz are 258.7μW and 638.4μW, respectively. Meanwhile, in the maximum frequency (400MHz) the pick to pick and RMS jitter of the suggested structure are 29.95ps and 8.67ps, correspondingly. Also, at the 400MHz and 150MHz the locking time is 1.75μs and 0.814μs, respectively. The active area of the PFD and proposed charge pump are 9.16×5.65μm² and 12.156.45μm², respectively. Simulation results of the proposed structure are simulated using the HSPICE BSIM3 model of a standard 0.18μm CMOS process.