Sampling-Induced Border Collision Bifurcation in a Voltage-Mode DPWM Synchronous Buck Converter

The output voltage of a voltage-mode digitally pulse-width-modulated (DPWM) dc-dc converter is sampled once per switching cycle, and past studies show the existence of limit cycle oscillations due to quantization. This brief reports that the map of a continuous conduction mode (CCM) buck converter under DPWM is shown to be discontinuous and exhibits border collision bifurcations mainly because of a sampling delay. The discrete-time state space is piecewise smooth, divided into nine regions with different functional forms and separated by eight boundaries. This is unlikely using analog PWM, in which only three regions and two borders exist under CCM. The closed-form stability conditions are derived and design methods are discussed to enhance the stability boundary. A prototype buck converter is tested. Experimental bifurcation diagrams and time domain results are demonstrated to support the analytical predictions.