Gate Leakage in Non-Volatile Ferroelectric Transistors: Device-Circuit Implications

Ferroelectric FETs (FEFETs) offer intriguing possibilities for the design of steep switching and non-volatile (NV) transistors [1]. FEFETs may be realized either: (i) with an internal metal layer (w-IML) between ferroelectric (FE e.g. HZO) and dielectric (DE) or (ii) direct integration of FE on DE without the use of internal metal (w/o-IML). Each of these devices have their own issues [2], [3]. FEFETs w/o-IML may be affected by defects in HZO (resulting in trapping/de-trapping [2]), and non-uniform FE electric fields (due to the underlying FET), which may lead to performance degradation/variability [4]. On the other hand, in FEFETs w-IML, the IML is floating and the gate leakage (GL) can result in several issues. The effect of GL in the context of steep switching of FEFETs has been discussed in [3]. Similarly, there is a need to understand the impact of GL in NV FEFETs. In this paper, we analyze the implications of gate leakage in NV FEFETs w-IML and describe how distinguishability between the two NV states can be lost due to GL. We propose gate workfunction (GWF) engineering along with a modified read scheme for FEFET based memory to counter the effect of GL.