Abstract:
InP double-heterojunction bipolar transistors (DHBTs) have demonstrated power gain cutoff frequencies (fmax) above 1THz under low collector voltage due to electron veloci...Show MoreMetadata
Abstract:
InP double-heterojunction bipolar transistors (DHBTs) have demonstrated power gain cutoff frequencies (fmax) above 1THz under low collector voltage due to electron velocity overshoot in the InP drift collector [1] [2]. Under higher collector voltage, however, a quick onset of Γ-L scattering limits the average electron velocity to the saturation velocity (Fig. 1(a)-(c)), leading to a Johnson's figure-of-merit (JFOM) second to GaN HEMTs and a limited transistor power bandwidth for InP DHBTs [3]. Here we propose a velocity-engineered device structure called the segmented-collector DHBT (SC-DHBT) that incorporates p-type scattering layers within the drift collector to reduce the electron kinetic energy and force a greater electron distribution into the low effective mass Γ- valley for extended velocity overshoot (Fig. 3(a)). Transport simulations show the collector transit time τc is reduced from 1.23ps in the reference design to 0.90ps in a double scatterer design at Vcb=5V, Jc= 1mA/um2. The proposed SC-DHBT design is suited for large power bandwidth power amplifiers.
Published in: 2018 76th Device Research Conference (DRC)
Date of Conference: 24-27 June 2018
Date Added to IEEE Xplore: 23 August 2018
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