Simulation Model and Environment for Mixed-Criticality Networked Multi-Core Chips

The requirement for networked multi-core systems is expanding dramatically in many domains such as, aerospace, industry 4.0 and automotive areas. Today's systems that implicate multi-cores, complex architectures and a big variety of applications require well-structured and hierarchical simulation environments. In addition, an efficient and early validation of system requirements during design phase and not during implementation or deployment phases is essential. This has led to a higher demand for simulation tools and environments that can meet the increasing expectations for simulation accuracy, real-time and mixed-criticality support. However, currently there is a gap between the mixed-criticality integration at chip-level and off-chip level, which is a challenge for upcoming mixed-criticality systems with multi-core chips. In this work, a hierarchical simulation environment for mixed-criticality systems based on multi-core chips is introduced. The presented simulation model utilizes criticality-aware interfaces and gateways throughout the different simulated system levels, and successfully combines different simulation tools for the scope of the simulated case realization. In addition, an avionic use-case is presented to validate the presented simulation environment.