A fault-tolerant evolvable face identification chip

We have developed a new design methodology for face identification chips using a genetic algorithm. In the design, face images are transformed to truth-tables and they are evolved to obtain generalization ability. Digital circuits are synthesized by using the evolved truth-tables. Parallelism in the data can be embedded in the circuits by this direct hardware implementation of the face images. A face identification chip prototype has been developed by synthesizing the evolved truth tables to logic circuits. The circuit size of the chip was 1334 gates for one person on average, and this was small enough to be implemented onto a standard FPGA (field programmable gate array) chip. The chip identified a face image at 400 ns and achieved an identification accuracy of 97.2% in average. Furthermore, a high identification accuracy of more than 90% was maintained even under 18% faulty gate ratio and this high fault tolerance degraded gracefully as the faulty gate ratio increased.