A Ku-band Phased Array in Package Integrating Four 180 nm CMOS Transceivers with On-chip Antennas

This paper presents a phased array, which is composed of four independent transceivers integrated with on-chip antennas. Every transceiver with an on-chip antenna is fabricated in a standard 180 nm CMOS process. To achieve a higher gain and sidelobe suppression level, an off-chip guard ring array is used. Considering the fabrication error, the influence of the length of bonding wire is studied. At 17 GHz, the phased array scanning region is ±28° with a 10 dB sidelobe suppression level, and ±32° with an 8.8 dB sidelobe suppression level. Meanwhile, the peak equivalent isotropic radiated power (EIRP) is 14 dBm. Every single transceiver with an on-chip antenna occupies 6.2x1.3 mm
²
, Besides, each receiver channel (RX) draws 114 mA from a 1.8V supply, while a transmitter channel (TX) consumes 145 mA from a 3.3V supply.