Pure Magnetic Logic Circuits: A Reliability Analysis

As CMOS technology downscales toward nanometer era, static power consumption due to transistor leakage currents and susceptibility to environmental noise like high-energy particles have become serious concerns. Nano-magnetic memory and logic elements have been proposed as a viable solution for hardening circuits against high-energy particles and overcoming the issue of increasing leakage power. This paper provides a comprehensive reliability analysis and comparison for different magnetic logic gate families. In addition, the cross effects of reliability, power consumption, and delay in the design of reliable magnetic logic gates are investigated and characterized.