Code compression as a variable in hardware/software co-design

We present a new way to practice and view hardware/software co-design: rather than raising the level of abstraction m order to exploit the highest possible degree of optimization, we use code compression i.e. we practice at the bit-level. Through our novel architecture combined with our compression methodology this results in optimization of all major design goals/constraints. In particular, we present a compression methodology that deploys what we call a "post-cache architecture" (i.e. the detached decompression unit is located between the CPU and the instruction cache). We present a design methodology that allows the designer to control parameters like speed, power, and area through the choice of compression parameters. In addition we show that our compression methodology (using a Markov Model) is more efficient than the widely used Huffman compression scheme.