Performance Optimization of Implementation of Lattice Boltzmann Method in ARUZ

The paper presents the performance optimization of implementation of the Lattice Boltzmann method on ARUZ, a massively parallel FPGA-based simulator located in Lodz, Poland. Compared to previous publications, a performance improvement of 46% has been achieved on D2Q9 lattice due to overlapping of communication with computation. The presented approach is suitable also for other cellular automata-based simulations. Extrapolation of results from the single ARUZ board suggests, that LBM simulation of 1080 \pmb×480 lattice on 18 panels of ARUZ would reach the performance of 302 10
³
MLUPS (Million Lattice Updates per Second).