Design of Matrix Controller for Hybrid Pixel Detectors

Hybrid pixel detectors used for radiation imaging consist of a pixelated semiconductor sensor connected to a readout ASIC with a pixel matrix of the same geometry. The achievable frame rate and possible applications of the detector depend heavily on the pixel matrix controlling logic and the chip-to-world interface. In this paper we present the design of a controller for a pixel matrix which provides timing control of the matrix with the resolution of 2.5 ns, and an effective output data rate of 12.8 Gbps, at 400 MHz system clock. The controller was implemented in 40 nm CMOS technology, connected to 64 × 64 matrix of 50 μm × 50 μm pixels.