High Resolution Latched Comparator Implemented in 22 nm FD-SOI Process

This paper presents the design of comparator dedicated for high linearity flash ADC, implemented in 22 nm FD-SOI process with 0.8 V supply. The block employs latched dynamic comparator preceded by two-stage preamplifier. The main obstacle to obtain high resolution comparator is transistors' mismatch resulting in relatively high offset voltage of the amplifier. Thus, compensation technique based on trimming of transistor's threshold voltage by means of modulating of back-gate polarization has been employed. The obtained comparator presents resolution of \pmb±3 mV.