A 20 DB Gain Two-Stage Low-Noise Amplifier with High Yield for 5 GHz Applications

This paper presents the design of a two-stage low-noise amplifier (LNA) in a standard 130 nm CMOS technology, operating around 5 GHz, and fully synthesized with an automatic yield-aware integrated circuit (IC) design flow. The topology described in this paper does not require external bias, and is composed of two common-source amplifying stages and a subsequent common-drain output buffer. Simulation results of a high yield solution achieved by AIDA-C, a state-of-the-art multiobjective circuit design tool, show that a forward gain of around 20 dB, with a noise figure around 2.25 dB and a 1.3 GHz bandwidth can be achieved with this topology, draining less than 7 mA from a 1 V voltage supply source. Finally, the results achieved in this work are compared with a set of previously published LNA topologies, proving the benefits of both the topology and the automatic IC design tool.