Modulation of Within-Wafer and Within-die Topography for Damascene Copper in Advanced Technology

A novel copper electroplating and CMP process was developed to effectively modulate the within-wafer and within-die nanoscale topography. The feasibility of this new metallization is demonstrated on a 64nm pitch product with an equivalent defect level, lower and tighter distribution in resistance and trench height. It's believed to be extendable to other advanced nodes for a sizable reduction in copper overburden which saves CMP polish cycle time from the plan-of-record time.