VLSI Design of Frequent Items Counting Using Binary Decoders Applied to 8-bit per Item Case-study

In this paper, the Very-Large-Scale Integration design of Frequent Items Counting (FIC) is proposed. The fundamental idea is to use binary decoders to generate a matrix of binary values of all input items, with each column represents for one items binary value. Then, the sums are executed on the rows of the matrix to retrieve the input items counting results. The proposed design is applied to the case-study of 8bit/item. That means 256 different types of items in total. For storing the counting results, various options of count-register are also presented. The proposed architecture is implemented with seven option of count-register from 8-bit counter to 32-bit counters, with the incremental of 4-bit at a time. The design was implemented on the Altera Arria V SoC Development Kit. After successful built and verified on Field Programmable Gate Array (FPGA), the design was synthesized using Synopsys tools with the process of SOTB (Silicon on Thin Buried-oxide) 65nm. The FPGA results achieved the average speed of 3,883.1 and 4,638.62 million item-counting per second for the 32-bit and 8-bit count-register options, respectively. Compared to our previous work and the software-based application, the achieved speed results are more than three times and more than 150 times faster, respectively. The SOTB-65nm builds achieved the theory speed about 75% of the average practical results of FPGA implementations.