Design, Fabrication and Characterization of TSV Interposer Integrated 3D Capacitor for SIP Applications

In this paper, TSV interposer integrated 3D high density capacitor is presented, which is featuring in a Metal-Insulation-Metal (MIM) structure on inside surface of blind TSVs array. A process is developed with Al
₂
O
₃
as insulation layer deposited by Atomic Layer Deposition (ALD). With this process, TSV interposer integrated high density 3D capacitor sample is fabricated, and characterized in terms of capacitance density, leakage current, breakdown voltage, Self-resonant frequency (SRF) and Equivalent series Resistance (ESR). According to the experiment, it has a capacitance density of 5nF/mm
²
, a leakage current less than 2.5μA at a bias voltage below 10V and a breakdown voltage about 20V, a predicted ESR about W and a ESR about MHz. The reason is investigated with simulation results and optimization direction is assured.