2.5D Glass Panel Embedded (GPE) Packages with Better I/O Density, Performance, Cost and Reliability than Current Silicon Interposers and High-Density Fan-Out Packages

This paper demonstrates for the first time a next generation high-bandwidth 2.5D glass panel embedding (GPE) architecture with better I/O density, performance, cost and reliability than silicon interposers and high density fan-out packages for heterogeneous integration. Silicon interposers were the first 2.5D technology to enter volume manufacturing, first with TSVs as CoWoS by TSMC and later as embedded bridge EMIB by Intel. High density fan-out packages by chip-first, such as InFO by TSMC, and RDL-first were recently developed. However, all current approaches face challenges in meeting future 2.5D I/O, performance, cost and reliability needs. This paper presents the first demonstration of a revolutionary new concept in scaling power-efficient bandwidth, cost, large package size and board-level reliability, called 2.5D glass panel embedding (GPE). High temperature and low CTE glass reduces die shifts from tens of microns in current molded fan-out to less than 2 microns in GPE. RDL connecting to embedded ICs with 1-2 micron lines and vias overcomes the solder thermo-compression bonding limitations. RDL with much lower resistance and capacitance than BEOL RDL continues power-efficient bandwidth scaling. Ultra-thin glass is readily available in large panels for lower cost. The tailorable CTE of glass allows for reliable direct SMT attach to board of large GPE packages. With a total package thickness of less than 200 microns, this paper describes the fabrication process for an ultra-thin 2.5D GPE, and a systematic parametric process optimization to reduce die shifts to less than 2 microns, leading to the first known demonstration of side-by-side embedding of HBM test chips with all-Cu interconnections at 40 micron I/O pitch.