A CMOS-SOI Power Amplifier Technology using EDNMOS for Sub 6 GHz Wireless Applications

Technology benchmarking results specific to power amplifiers (PA) application designed using extended drain NMOS (EDNMOS) on SOI is presented. Improved kink free conductance characteristics of this device leads to superior performance when the optimized EDNMOS is used standalone as a PA output stage or in a cascode arrangement with other faster devices. The CMOS technology with this device is a viable alternative for designing watt level power amplifier on SOI.